EP194中文资料4-Lane cLVDS Receiver with 4 Ports LVDS Outputs数据手册Explore规格书

特性 Features

•Support up-to 135 Mhz pixel rate at 10-bit color depth per cLVDS input lane (5.4G bps per lane).•Support up-to 150 Mhz pixel rate per LVDS output port (150 Mhz LVDS clock per port).•Support 2 data maps for LVDS output•Support 6/8/10-bit color depth in both cLVDS inputs and LVDS outputs•Support 3-byte, 4-byte, and 5-byte Data Packing mode in cLVDS receiver•Can be cascaded with clock synchronization mechanism to extend number of cLVDS input lanes and LVDS output ports.•Programmable cLVDS input lane and pin sequence for easy PCB layout.•Programmable LVDS output port swapping for easy PCB layout.•Programmable Control Registers through IIC interface•1.2V and 3.3V power required•Supports Power Down Mode•128-pin LQFP
 
Block Diagram