EP149中文资料8-Lane cLVDS Transmitter with 4-Port LVDS or Digital Inputs数据手册Explore规格书

特性 Features

•Programmable Digital input or LVDS inputs•Support up-to 150 Mhz pixel rate per LVDS input port.•Support up-to 75 Mhz pixel rate per cLVDS output lane.•Support 2 data maps for LVDS input•Support DE_ONLY video timing for LVDS input•Support flexible LVDS Port Swap feature for easy PCB layout•Support 8-bit and 10-bit color depth in both Digital/LVDS inputs and cLVDS outputs•Support 3-byte, 4-byte, and 5-byte Data Packing mode in cLVDS transmitter•Programmable 4-lane or 8-lane cLVDS outputs•Can be cascaded to extend LVDS input ports with clock synchronization mechanism.•Flexible LVDS input port to cLVDS output lane mapping.•Programmable Control Registers through IIC interface•1.8V and 3.3V power required•Supports Power Down Mode•128-pin LQFP package
 
Block Diagram