Horizontal Genlock, 4FSC

The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

文件：313.88 Kbytes 页数：15 Pages

Intersil

Horizontal Genlock, 4FSC

The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

文件：731.74 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：EL4584CN；Package：16LdPDIP；Horizontal Genlock, 4FSC

The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

文件：731.74 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：EL4584CS；Package：16LdSOIC；Horizontal Genlock, 4FSC

The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

文件：731.74 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：EL4584CSZ；Package：16LdSOIC；Horizontal Genlock, 4FSC

The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

文件：731.74 Kbytes 页数：15 Pages

RENESAS

瑞萨

Horizontal Genlock, 4FSC

The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to it. • 36MHz, general purpose PLL\n•4FSCbased timing (use the EL4585 for 8FSC)\n• Compatible with EL4583 sync separator\n• VCXO, Xtal, or LC tank oscillator\n• < 2ns jitter (VCXO)\n• User controlled PLL capture and lock\n• Compatible with NTSC and PAL TV formats\n• 8 pre-programmed TV scan rate clock div;

Renesas

瑞萨

Horizontal Genlock, 4 FSC

General Description The EL4584C is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rat

文件：275.82 Kbytes 页数：16 Pages

Elantec

Horizontal Genlock, 4 FSC

General Description The EL4584C is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rat

文件：275.82 Kbytes 页数：16 Pages

Elantec

Horizontal Genlock, 4FSC

The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

文件：313.88 Kbytes 页数：15 Pages

Intersil

Horizontal Genlock, 4FSC

The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to i

文件：313.88 Kbytes 页数：15 Pages

Intersil