EDI88512LPXCC中文资料WEDC数据手册PDF规格书

The EDI88512C is a 4 megabit Monolithic CMOS Static RAM.

The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. Both the DIP and CSOJ packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128C. Pins 1 and 30 become the higher order addresses.

A Low Power version with Data Retention (EDI88512LP) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535.

FEATURES

■ 512Kx8 bit CMOS Static

■ Random Access Memory

• Access Times of 70, 85, 100ns

• Data Retention Function (LP version)

• TTL Compatible Inputs and Outputs

• Fully Static, No Clocks

■ 32 lead JEDEC Approved Evolutionary Pinout

• Ceramic Sidebrazed 600 mil DIP (Package 9)

• Ceramic SOJ (Package 140)

■ Single +5V (±10) Supply Operation