128Kx8 MONOLITHIC SRAM, SMD 5962-89598

The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8. The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied. The second chip select line (

文件：387.07 Kbytes 页数：8 Pages

WEDC

128Kx8 MONOLITHIC SRAM, SMD 5962-89598

The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8. The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied. The second chip select line (

文件：387.07 Kbytes 页数：8 Pages

WEDC

128Kx8 MONOLITHIC SRAM, SMD 5962-89598

The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8. The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied. The second chip select line (

文件：387.07 Kbytes 页数：8 Pages

WEDC

128Kx8 MONOLITHIC SRAM, SMD 5962-89598

The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8. The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied. The second chip select line (

文件：387.07 Kbytes 页数：8 Pages

WEDC

128Kx8 Monolithic SRAM, SMD 5962-89598

The device has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. A Low Power

文件：464.21 Kbytes 页数：9 Pages

WEDC

128Kx8 Monolithic SRAM, SMD 5962-89598

The device has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. A Low Power

文件：464.21 Kbytes 页数：9 Pages

WEDC