1G bits DDR2 SDRAM

EDE1108AJBG (128M words ×8 bits)\nEDE1116AJBG (64M words ×16 bits) • Double-data-rate architecture; two data transfers per clock cycle\n• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture\n• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver\n• DQS is edge-;

Micron

美光

1G bits DDR2 SDRAM

• Double-data-rate architecture; two data transfers per clock cycle\n• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture\n• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at\nthe receiver\n• DQS is edge;

Micron

美光

1G bits DDR2 SDRAM

Micron

美光