EBE10RD4ABFA数据手册Micron中文资料规格书

描述 Description

The EBE10RD4ABFA is a 128M words × 72 bits, 1 rank DDR2 SDRAM Module, mounting 18 pieces of DDR2 SDRAM sealed in FBGA (µBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design.

特性 Features

• 240-pin socket type dual in line memory module (DIMM)
 PCB height: 30.0mm
 Lead pitch: 1.0mm
 Lead-free
• 1.8V power supply
• Data rate: 533Mbps/400Mbps (max.)
• 1.8 V (SSTL_18 compatible) I/O
• Double-data-rate architecture: two data transfers per clock cycle
• Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in capturing data at the receiver
• DQS is edge aligned with data for READs; center aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data referenced to both edges of DQS
• Four internal banks for concurrent operation (Component)
• Burst length: 4, 8
• /CAS latency (CL): 3, 4, 5
• Auto precharge option for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
• Posted CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe operation
• 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)