EBD11ED8ABFB-7B中文资料尔必达数据手册PDF规格书

描述 Description

The EBD11ED8ABFB is 128M words × 72 bits, 2 banks Double Data Rate (DDR) SDRAM unbuffered module, mounted 18 pieces of 512M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.

特性 Features

• 184-pin socket type dual in line memory module (DIMM)

- PCB height: 31.75mm

- Lead pitch: 1.27mm

• 2.5V power supply

• Data rate: 333Mbps/266Mbps (max.)

• 2.5 V (SSTL_2 compatible) I/O

• Double Data Rate architecture; two data transfers per clock cycle

• Bi-directional, data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver

• Data inputs and outputs are synchronized with DQS

• 4 internal banks for concurrent operation (Component)

• DQS is edge aligned with data for READs; center aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data referenced to both edges of DQS

• Auto precharge option for each burst access

• Programmable burst length: 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5

• Refresh cycles: (8192 refresh cycles /64ms)

- 7.8µs maximum average periodic refresh interval

• 2 variations of refresh

- Auto refresh

- Self refresh