DSP56853E中文资料飞思卡尔数据手册PDF规格书

56853 General Description

• 120 MIPS at 120MHz

• 12K x 16-bit Program SRAM

• 4K x 16-bit Data SRAM

• 1K x 16-bit Boot ROM

• Access up to 2M words of program memory or 8M of data memory

• Chip Select Logic for glue-less interface to ROM and SRAM

• Six (6) independent channels of DMA

• Enhanced Synchronous Serial Interfaces (ESSI)

• Two (2) Serial Communication Interfaces (SCI)

• Serial Port Interface (SPI)

• 8-bit Parallel Host Interface

• General Purpose 16-bit Quad Timer

• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging

• Computer Operating Properly (COP)/Watchdog Timer

• Time-of-Day (TOD)

• 128 LQFP package

• Up to 41 GPIO

56853 Features

Core

• Efficient 16-bit engine with dual Harvard architecture

• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four (4) 36-bit accumulators including extension bits

• 16-bit bidirectional shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three (3) internal address buses and one (1) external address bus

• Four (4) internal data buses and one (1) external data bus

• Instruction set supports both DSP and controller functions

• Four (4) hardware interrupt levels

• Five (5) software interrupt levels

• Controller-style addressing modes and instructions for compact code

• Efficient C Compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced OnCE debug programming interface