INTERGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

文件：239.95 Kbytes 页数：4 Pages

FREESCALEFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

16-BIT DIGITAL SIGNAL PROCESSOR

文件：247.9 Kbytes 页数：4 Pages

FREESCALEFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructio

文件：1.27961 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR

FEATURES RISC M¥CORE MCU ¥ 32-bit load/store RISC architecture ¥ Fixed 16-bit instruction length ¥ 16-entry 32-bit general-purpose register file ¥ 32-bit internal address and data buses ¥ Efficient four-stage, fully interlocked execution pipeline ¥ Single-cycle execution for most instructio

文件：1.13755 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR

FEATURES RISC M¥CORE MCU ¥ 32-bit load/store RISC architecture ¥ Fixed 16-bit instruction length ¥ 16-entry 32-bit general-purpose register file ¥ 32-bit internal address and data buses ¥ Efficient four-stage, fully interlocked execution pipeline ¥ Single-cycle execution for most instructio

文件：1.13755 Mbytes 页数：76 Pages

恩XP

INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

FEATURES RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructio

文件：1.27961 Mbytes 页数：76 Pages

恩XP