DSLVDS1002数据手册TI中文资料规格书

描述 Description

The DSLVDS1002 is a single channel Low Voltage Differential Signaling (LVDS) receiverdesigned for applications requiring low power dissipation, low noise and high data rates. Inaddition, the short circuit fault current is also minimized. The DSLVDS1002 device is designed tosupport data rates that are at least 400 Mbps (200 MHz) utilizing LVDS technology.
The DSLVDS1002 accepts low voltage (±350-mV typical) differential input signals andoutputs a 3.3-V CMOS/TTL signal. The receivers also support open, shorted, and terminated (100 Ω)input fail-safe. The receiver output will be HIGH for all fail-safe conditions. The DSLVDS1002 isin a 5-lead SOT-23 package that is designed for easy PCB layout.
The DSLVDS1002 can be paired with its companion single line driver, DSLVDS1001, or withany LVDS driver, to provide a high-speed LVDS Interference.

特性 Features

• 旨在用于信号传输速率高达 400Mbps 的应用
• 单个 3.3V 电源设计（3V 至 3.6V 的范围）
• 100ps 典型差动偏斜
• 3.5ns 最大传播延迟
• 接受小摆幅差动信号电平
• 断电保护（LVDS 输入端具有高阻抗）
• 直通引脚排列可简化 PCB 布局
• 低功耗（3.3V 典型电源时为 10mW）
• LVDS 接收器输入端接受 LVDS/BLVDS/LVPECL 输入
• 针对开路、短路和终止输入的失效防护保护
• 5 引脚 SOT-23 封装
• 符合或超出 ANSI TIA/EIA-644-A 标准
• 工业工作温度范围（−40°C 至 +85°C）