DS92001TMAXSLASHNOPB.A中文资料德州仪器数据手册PDF规格书

FEATURES

• Single +3.3 V Supply

• Receiver Inputs Accept LVDS/CML/LVPECL

Signals

• TRI-STATE Outputs

• Receiver Input Threshold < ±100 mV

• Fast Propagation Delay of 1.4 ns (typ)

• Low Jitter 400 Mbps Fully Differential Data

Path

• Compatible with BLVDS 10-bit SerDes (40MHz)

• Compatible with ANSI/TIA/EIA-644-A LVDS

Standard

• Available in SOIC and Space Saving WSON

Package

• Industrial Temperature Range

DESCRIPTION

The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS

input signal and provides a BLVDS output signal. In

many large systems, signals are distributed across

backplanes. One of the limiting factors for system

speed is the stub length or the distance between

the transmission line and the unterminated receivers

on individual cards. Although it is generally

recognized that this distance should be as short as

possible to maximize system performance, real-world

packaging concerns often make it difficult to make the

stubs as short as the designer would like.

The DS92001 has edge transitions optimized for

multidrop backplanes where the switching frequency

is in the 200 MHz range or less. The output edge rate

is critical in some systems where long stubs may be

present, and utilizing a slow transition allows for

longer stub lengths.

The DS92001, available in the WSON package, will

allow the receiver inputs to be placed very close to

the main transmission line, thus improving system

performance.

A wide input dynamic range allows the DS92001 to

receive differential signals from LVPECL, CML as

well as LVDS sources. This will allow the device to

also fill the role of an LVPECL-BLVDS or CMLBLVDS

translator.