DS90UH925Q-Q1中文资料德州仪器数据手册PDF规格书

1 Features

1• Integrated HDCP Cipher Engine with On-chip Key

Storage

• Bidirectional Control Interface Channel Interface

with I2C Compatible Serial Control Bus

• Supports High Definition (720p) Digital Video

Format

• RGB888 + VS, HS, DE and I2S Audio Supported

• 5 to 85 MHz PCLK Supported

• Single 3.3V Operation with 1.8 V or 3.3 V

Compatible LVCMOS I/O Interface

• AC-coupled STP Interconnect up to 10 meters

• Parallel LVCMOS Video Inputs

• DC-balanced & Scrambled Data with Embedded

Clock

• HDCP Content Protected

• Supports HDCP Repeater Application

• Internal Pattern Generation

• Low Power Modes Minimize Power Dissipation

• Automotive Grade Product: AEC-Q100 Grade 2

Qualified

• > 8k V HBM and ISO 10605 ESD rating

• Backward Compatible Modes

2 Applications

• Automotive Display for Navigation

• Rear Seat Entertainment Systems

3 Description

The DS90UH925Q-Q1 serializer, in conjunction with

the DS90UH926Q-Q1 deserializer, provides a

solution for secure distribution of content-protected

digital video within automotive entertainment

systems. This chipset translates a parallel RGB Video

Interface into a single pair high-speed serialized

interface. The digital video data is protected using the

industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video

and audio data transmission and full duplex control

including I2C communication over a single differential

link. Consolidation of video data and control over a

single differential pair reduces the interconnect size

and weight, while also eliminating skew issues and

simplifying system design.

The DS90UH925Q-Q1 serializer embeds the clock,

content protects the data payload, and level shifts the

signals to high-speed low voltage differential

signaling. Up to 24 RGB data bits are serialized along

with three video control signals and up to two I2S

data inputs.

EMI is minimized by the use of low voltage differential

signaling, data scrambling and randomization and spread spectrum clocking compatibility.

The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in

on-chip memory.