DS90UB927QSQSLASHNOPB中文资料德州仪器数据手册PDF规格书

1 Features

1• Bidirectional Control Channel Interface with I2Ccompatible

Serial Control Bus

• Low EMI FPD-Link Video Input

• Supports High Definition (720p) Digital Video

Format

• 5-MHz to 85-MHz PCLK Supported

• RGB888 + VS, HS, DE and I2S Audio Supported

• Up to 4 I2S Digital Audio Inputs for Surround

Sound Applications

• 4 Bidirectional GPIO Channels with 2 Dedicated

Pins

• Single 3.3-V Supply with 1.8-V or 3.3-V

Compatible LVCMOS I/O Interface

• AC-Coupled STP Interconnect Up to 10 Meters

• DC-Balanced and Scrambled Data With

Embedded Clock

• Supports Repeater Application

• Internal Pattern Generation

• Low Power Modes Minimize Power Dissipation

• Automotive Grade Product: AEC-Q100 Grade 2

Qualified

• >8-kV HBM and ISO 10605 ESD Rating

• Backward Compatible Modes

2 Applications

• Automotive Displays for Navigation

• Rear Seat Entertainment Systems

• Automotive Driver Assistance

• Automotive Megapixel Camera Systems

3 Description

The DS90UB927Q-Q1 serializer, in conjunction with a

DS90UB928Q-Q1 or DS90UB926Q-Q1 deserializer,

provides a complete digital interface for concurrent

transmission of high-speed video, audio, and control

data for automotive display and image sensing

applications.

The chipset is ideally suited for automotive video

display systens with HD formats and automotive

vision systems with megapixel resolutions. The

DS90UB927Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO

controls. This device translates a FPD-Link video

interface into a single-pair high-speed serialized

interface. The FPD-Link III serial bus scheme

supports full duplex, high speed forward channel data

transmission and low-speed back channel communication over a single differential link.

Consolidation of audio, video, and control data over a

single differential pair reduces the interconnect size

and weight, while also eliminating skew issues and

simplifying system design.

The DS90UB927Q-Q1 serializer embeds the clock

and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along

with three video control signals, and up to four I2S

data inputs.

The FPD-Link data interface allows for easy

interfacing with data sources while also minimizing

EMI and bus width. EMI on the high-speed FPD-Link

III bus is minimized using low voltage differential

signaling, data scrambling and randomization, and DC-balancing.