DS90UB902QSQXSLASHNOPB中文资料德州仪器数据手册PDF规格书

1FEATURES

2• 10 MHz to 43 MHz Input PCLK Support

• 160 Mbps to 688 Mbps Data Throughput

• Single Differential Pair Interconnect

• Bidirectional Control Interface Channel with

I2C Support

• Embedded Clock with DC Balanced Coding to

Support AC-Coupled Interconnects

• Capable to Drive up to 10 Meters Shielded

Twisted-Pair

• I2C Compatible Serial Interface

• Single Hardware Device Addressing Pin

• 16-bit Data Payload with CRC (Cyclic

Redundancy Check) for Checking Data

Integrity

• Up to 6 Programmable GPIO's

• LOCK Output Reporting Pin and AT-SPEED

BIST Diagnosis Feature to Validate Link

Integrity

• Integrated Termination Resistors

• 1.8V- or 3.3V-Compatible Parallel Bus Interface

• Single Power Supply at 1.8V

• ISO 10605 ESD and IEC 61000-4-2 ESD

Compliant

• Automotive Grade Product: AEC-Q100 Grade 2

Qualified

• Temperature Range −40°C to +105°C

• No Reference Clock Required on Deserializer

• Programmable Receive Equalization

• EMI/EMC Mitigation

– DES Programmable Spread Spectrum

(SSCG) Outputs

– DES Receiver Staggered Outputs

APPLICATIONS

• Automotive Vision Systems

• Rear View, Side View Camera

• Lane Departure Warning

• Parking Assistance

• Blind Spot View

DESCRIPTION

The DS90UB901Q/DS90UB902Q chipset offers a

FPD-Link III interface with a high-speed forward

channel and a bidirectional control channel for data

transmission over a single differential pair. The

Serializer/Deserializer pair is targeted for direct

connections between automotive camera systems

and Host Controller/Electronic Control Unit (ECU).

The primary transport sends 16 bits of image data

over a single high-speed serial stream together with a

low latency bidirectional control channel transport that

supports I2C. Included with the 16-bit payload is a

selectable data integrity option for CRC (Cyclic

Redundancy Check) to monitor transmission link

errors. Using TI’s embedded clock technology allows

transparent full-duplex communication over a single

differential pair, carrying asymmetrical bidirectional

control information without the dependency of video

blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and

cable by eliminating the skew problems between

parallel data and clock paths. This significantly saves

system cost by narrowing data paths that in turn

reduce PCB layers, cable width, and connector size

and pins.

In addition, the Deserializer inputs provide

equalization control to compensate for loss from the

media over longer distances. Internal DC balanced

encoding/decoding is used to support AC-Coupled

interconnects.

A Serializer standby function provides a low power-

savings mode with a remote wake up capability for

signaling of a remote device.

The Serializer is offered in a 32-pin WQFN (5mm x

5mm) package, and Deserializer is offered in a 40-pin

WQFN (6mm x 6mm) package.