DS90LV110T数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz. The DS90LV110 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.The LVDS outputs can be put into TRI-STATE by use of the enable pin. For more details, please refer to the Application Information section of this datasheet.

DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz. The DS90LV110 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.The LVDS outputs can be put into TRI-STATE by use of the enable pin. For more details, please refer to the Application Information section of this datasheet.

特性 Features

• Low jitter 800 Mbps fully differential data path
• 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps
• Single +3.3 V Supply
• Less than 413 mW (typ) total power dissipation
• Balanced output impedance
• Output channel-to-channel skew is 35ps (typ)
• Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load.
• LVDS receiver inputs accept LVPECL signals
• Fast propagation delay of 2.8 ns (typ)
• Receiver input threshold