DS90LV110T集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

DS90LV110T属于集成电路（IC）的时钟缓冲器驱动器。由德州仪器制造生产的DS90LV110T时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。

1FEATURES

2• Low jitter 800 Mbps fully differential data path

• 145 ps (typ) of pk-pk jitter with PRBS = 223−1

data pattern at 800 Mbps

• Single +3.3 V Supply

• Less than 413 mW (typ) total power dissipation

• Balanced output impedance

• Output channel-to-channel skew is 35ps (typ)

• Differential output voltage (VOD) is 320mV (typ)

with 100Ω termination load.

• LVDS receiver inputs accept LVPECL signals

• Fast propagation delay of 2.8 ns (typ)

• Receiver input threshold < ±100 mV

• 28 lead TSSOP package

• Conforms to ANSI/TIA/EIA-644 LVDS standard

DESCRIPTION

DS90LV110 is a 1 to 10 data/clock distributor utilizing

LVDS (Low Voltage Differential Signaling) technology

for low power, high speed operation. Data paths are

fully differential from input to output for low noise

generation and low pulse width distortion. The design

allows connection of 1 input to all 10 outputs. LVDS

I/O enable high speed data transmission for point-to-

point interconnects. This device can be used as a

high speed differential 1 to 10 signal distribution /

fanout replacing multi-drop bus applications for higher

speed links with improved signal quality. It can also

be used for clock distribution up to 400MHz.

The DS90LV110 accepts LVDS signal levels,

LVPECL levels directly or PECL with attenuation

networks.

The LVDS outputs can be put into TRI-STATE by use

of the enable pin.

For more details, please refer to the APPLICATION

INFORMATION section of this datasheet.