丝印：DS90CR481VJD；Package：TQFP(NEZ)；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21613 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR481VJD；Package：TQFP；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21572 Mbytes 页数：26 Pages

TI

德州仪器

丝印：DS90CR481VJD；Package：TQFP(NEZ)；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21613 Mbytes 页数：26 Pages

TI

德州仪器

48 位 LVDS 频道链接串行器 - 65 - 112MHz

The DS90CR481 transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link. Every cycle of the transmit clock 48 bits of input data are sampled an • 3.168 Gbits/sec Bandwidth with 66 MHz Clock\n• 5.376 Gbits/sec Bandwidth with 112 MHz Clock\n• 65 - 112 MHz Input Clock Support \n• LVDS SER/DES Reduces Cable and Connector Size\n• Pre-Emphasis Reduces Cable Loading Effects\n• Optional DC Balance Encoding Reduces ISI Distortion\n• Cable Deskew of ;

TI

德州仪器

DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

文件：1.21613 Mbytes 页数：26 Pages

TI

德州仪器

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：899.87 Kbytes 页数：21 Pages

NSC

国半

48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz

文件：1.6522 Mbytes 页数：25 Pages

TI

德州仪器

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：904.79 Kbytes 页数：21 Pages

NSC

国半

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：899.87 Kbytes 页数：21 Pages

NSC

国半

48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz

文件：1.6522 Mbytes 页数：25 Pages

TI

德州仪器