DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link??6 MHz, 3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link??6 MHz

文件：250.02 Kbytes 页数：12 Pages

NSC

国半

3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHz, 3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link-66 MHz

文件：378.71 Kbytes 页数：14 Pages

NSC

国半

3.3-V Rising Edge Data Strobe LVDS Receiver

文件：2.40138 Mbytes 页数：34 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器

丝印：DS90CR286AMTD；Package：TSSOP(DGG)；DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz

1 Features 1• 20 to 66 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best–in–Class Set and Hold Times on Rx Outputs • Rx Power Consumption 7 kV (HBM), > 700 V (EIAJ) • PLL Requi

文件：2.14899 Mbytes 页数：38 Pages

TI

德州仪器