DS90CR218AMTDSLASHNOPB.A中文资料德州仪器数据手册PDF规格书

1FEATURES

• 12 to 85 MHz Shift Clock Support

• 50% Duty Cycle on Receiver Output Clock

• Low Power Consumption

• ±1V Common-mode Range (Around +1.2V)

• Narrow Bus Reduces Cable Size and Cost

• Up to 1.785 Gbps Throughput

• Up to 223 Mbytes/sec Bandwidth

• 345 mV (typ) Swing LVDS Devices for Low EMI

• PLL Requires No External Components

• Rising Edge Data Strobe

• Compatible with TIA/EIA-644 LVDS Standard

• Low Profile 48-Lead TSSOP Package.

DESCRIPTION

The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output

data. When operating at the maximum input clock

rate of 85 Mhz, the LVDS data is received at 595

Mbps per data channel for a total data throughput of

1.785 Gbit/sec (233 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and

cable size problems associated with wide, high-speed

TTL interfaces.