DS90CF564MTD/NOPB.A中文资料德州仪器数据手册PDF规格书

1FEATURES

2• 20 to 65 MHz Shift Clk Support

• Up to 171 Mbytes/s Bandwidth

• Cable Size is Reduced to Save Cost

• 290 mV Swing LVDS Devices for Low EMI

• Low Power CMOS Design (< 550 mW typ)

• Power-down Mode Saves Power (< 0.25 mW)

• PLL Requires No External Components

• Low Profile 48-Lead TSSOP Package

• Falling Edge Data Strobe

• Compatible with TIA/EIA-644 LVDS Standard

• Single Pixel Per Clock XGA (1024 x 768)

• Supports VGA, SVGA, XGA and Higher

• 1.3 Gbps Throughput

DESCRIPTION

The DS90CF563 transmitter converts 21 bits of

CMOS/TTL data into three LVDS (Low Voltage

Differential Signaling) data streams. A phase-locked

transmit clock is transmitted in parallel with the data

streams over a fourth LVDS link. Every cycle of the

transmit clock 21 bits of input data are sampled and transmitted. The DS90CF564 receiver converts the

LVDS data streams back into 21 bits of CMOS/TTL

data. At a transmit clock frequency of 65 MHz, 18 bits

of RGB data and 3 bits of LCD timing and control

data (FPLINE, FPFRAME, DRDY) are transmitted at

a rate of 455 Mbps per LVDS data channel. Using a

65 MHz clock, the data throughput is 171 Mbytes per

second. These devices are offered with falling edge

data strobes for convenient interface with a variety of

graphics and LCD panel controllers.

This chipset is an ideal means to solve EMI and

cable size problems associated with wide, high speed

TTL interfaces.