DS90CF383MTDSLASHNOPB.B中文资料德州仪器数据手册PDF规格书

General Description

The DS90CF383 transmitter converts 28 bits of CMOS/TTL

data into four LVDS (Low Voltage Differential Signaling) data

streams. A phase-locked transmit clock is transmitted in parallel

with the data streams over a fifth LVDS link. Every cycle

of the transmit clock 28 bits of input data are sampled and

transmitted. At a transmit clock frequency of 65 MHz, 24 bits

of RGB data and 3 bits of LCD timing and control data

(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455

Mbps per LVDS data channel. Using a 65 MHz clock, the

data throughputs is 227 Mbytes/sec.

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high speed TTL interfaces.

特性 Features

20 to 65 MHz shift clock support

Single 3.3V supply

Chipset (Tx + Rx) power consumption < 250 mW (typ)

Power-down mode (< 0.5 mW total)

Single pixel per clock XGA (1024x768) ready

Supports VGA, SVGA, XGA and higher addressability.

Up to 227 Megabytes/sec bandwidth

Up to 1.8 Gbps throughput

Narrow bus reduces cable size and cost

290 mV swing LVDS devices for low EMI

PLL requires no external components

Low profile 56-lead TSSOP package

Falling edge data strobe Transmitter

Compatible with TIA/EIA-644 LVDS standard

ESD rating > 7 kV

Operating Temperature: −40°C to +85°C