DS90C387RVJDSLASHNOPB中文资料德州仪器数据手册PDF规格书

1FEATURES

2• Complies with Open LDI Specification for

Digital Display Interfaces

• 25 to 85MHz Clock Support

• Supports VGA through UXGA Panel

Resolution

• Up to 4.76Gbps Bandwidth in Dual 24-bit RGB

In-to-Dual Pixel Out Application

• Dual 12-bit Double Pumped Input DVO Port

• Pre-Emphasis Reduces Cable Loading Effects

• Drives Long, Low Cost Cables

• DC Balance Data Transmission Provided by

Transmitter Reduces ISI Distortion

• Transmitter Rejects Cycle-to-Cycle Jitter (±2ns

of Input Bit Period)

• Support both LVTTL and Low Voltage Level

Input (Capable of 1.0 to 1.8V)

• Two-Wire Serial Communication Interface up

to 400 KHz pin•

Programmable Input Clock and Control Strobe

Select

• Backward Compatible Configuration with

112MHz LDI and FPD-Link inter•

Optional Second LVDS Clock for Backward

Compatibility with FPD-Link Receivers

• Compatible with TIA/EIA-644

DESCRIPTION

The DS90C387R transmitter is designed to support

pixel data transmission from a Host to a Flat Panel

Display up to UXGA resolution. It is designed to be

compatible with Graphics Memory Controller Hub

(GMCH) by implementing two data per clock and can

be controlled by a two-wire serial communication

interface. Two input modes are supported: one port of

12-bit( two data per clock) input for 24-bit RGB, and two ports of 12-bit( two data per clock) input for dual

24-bit RGB( 48-bit total). In both modes, input data

will be clocked on both rising and falling edges in

LVTTL level operation, or clocked on the cross over of differential clock signals in the low swing operation.

Each input data width will be 1/2 of clock cycle. With

an input clock at 85MHz and input data at 170Mbps,

the maximum transmission rate of each LVDS line is

595Mbps, for a aggregate throughput rate of

2.38Gbps/4.76Gbps. It converts 24/48 bits

(Single/Dual Pixel 24-bit color) of data into 4/8 LVDS (Low Voltage Differential Signaling) data streams.

DS90C387R can be programmed via the two-wire

serial communication interface. The LVDS output pin•

out is identical to DS90C387. Thus, this transmitter

can be paired up with DS90CF388, receiver of the 112MHz LDI chipset or FPD-Link Receivers in non-

DC Balance mode operation which provides GUI/LCD

panel/mother board vendors a wide choice of inter•

operation with LVDS based TFT panels.

DS90C387R also comes with features that can be

found on DS90C387. Cable drive is enhanced with a

user selectable pre-emphasis feature that provides

additional output current during transitions to

counteract cable loading effects. DC Balancing on a

cycle-to-cycle basis is also provided to reduce ISI

(Inter-Symbol Interference), control signals (VSYNC,

HSYNC, DE) are sent during blanking intervals. With

pre-emphasis and DC Balancing, a low distortion eyepattern

is provided at the receiver end of the cable.

These enhancements allow cables 5 to 15+ meters in

length to be driven depending on media characteristic

and pixel clock speed. Pre-emphasis is available in

both the DC Balanced and Non-DC Balanced modes.

In the Non-DC Balanced mode backward

compatibility with FPD-Link Receivers is obtained.