Quad Unified Bus Transceiver

文件：78.13 Kbytes 页数：5 Pages

NSC

国半

Quad Unified Bus Transceiver

General Description\nThe DS8641 is a quad high speed drivers/receivers designed for use in bus organized data transmission systems interconnected by terminated 120Ω impedance lines. The external termination is intended to be a 180Ω resistor from the bus to the +5V logic supply together with a 390Ω r ■ 4 separate driver/receiver pairs per package\n■ Guaranteed minimum bus noise immunity of 0.6V, 1.1V typ\n■ Temperature insensitive receiver thresholds track bus logic levels\n■ 30 µA typical bus terminal current with normal VCC or with VCC = 0V\n■ Open collector driver output allows wire-OR connec;

TI

德州仪器

Quad Unified Bus Transceiver

文件：78.13 Kbytes 页数：5 Pages

NSC

国半

Integrated Host Processor Hardware Specifications

文件：1.69978 Mbytes 页数：140 Pages

FREESCALEFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

Integrated Host Processor Hardware Specifications

文件：1.69978 Mbytes 页数：140 Pages

FREESCALEFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

10/100/1000BASE-T PHY with RGMII and GMII MAC Interface

General Description Designed for high-performance, low-power, and low-cost Gigabit Ethernet, the VSC8601 and VSC8641 are the industry’s lowest-power and most highly integrated Gigabit Ethernet (GbE) PHYs. The VSC8601 is optimized for Gigabit LAN on Motherboard (GLOM) and Gigabit Ethernet switch a

文件：460.47 Kbytes 页数：2 Pages

VITESSE