DS32EL0124中文资料具有 DDR LVDS 并行接口的 125MHz 至 312.5MHz FPGA-Link 解串器数据手册TI规格书

描述 Description

The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface. The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.

特性 Features

• 5-bit DDR LVDS Parallel Data Interface
• Selectable DC-Balance Decoder
• Remote Sense for Automatic Detection and Negotiation of Link Status
• LVDS Parallel Interface
• Supports Output Data-Valid Signaling
• On Chip LC VCOs
• Retimed Serial Output (ELX device only)
• Configurable via SMBus
• 48-pin WQFN Package with Exposed DAP
• 1.25 to 3.125 Gbps Serial Data Rate
• -40° to +85°C Temperature Range
• 0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)

简介

DS32EL0124属于集成电路（IC）的串行器解串器。由TI制造生产的DS32EL0124串行器，解串器串行器将并行提供的信息转换为较高符号率的串行数据流，从而减少数字信息传输所需的导线数量；解串器执行相反的功能。常用于在图像传感器、图像处理器和显示器之间传输视频数据，还有针对工业 I/O 设备等其他应用而定制的器件。