DS28E54+T中文资料亚德诺数据手册PDF规格书

特性 Features

• DS2431/DS28E07 Reverse Compatibility

• 2.25Kbits of EEPROM Memory Partitioned into

11 User Pages of 256 Bits (First Five Pages

Compatible)

• 64-Bit Scratchpad Buffer for Compatible Secure

Writing with Offset and Individual Addressing

• ±8kV HBM ESD Protection (typ) for IO Pin

• Efficient Secure Hash Algorithm to Authenticate

Peripherals

• FIPS 202-Compliant SHA-3 Algorithm for

Challenge/Response Authentication and Device

Disable

• FIPS 198-Compliant Keyed-Hash Message

Authentication Code (HMAC)

• Optional HMAC SHA3-256 Authenticated Write

Protection of EEPROM

• Supplemental Features for Easy Integration into End

Applications

• 17-Bit, One-Time Settable, Nonvolatile

Decrement-Only Counter with Authenticated

Read

• Secure Storage for Secret

• 2.25KBits of Secure EEPROM for User Data and

Secret

• Unique and Unalterable, Factory-Programmed,

64-Bit Identification Number (ROM ID)

• Advanced 1-Wire Protocol Minimizes Interface to

Single Contact

• Standard and Overdrive Communication Speed

• Internal Parasite Power Capacitor

• Operating Range: 2.8V to 5.25V, -40°C to +85°C

• SFN, SFN 6x6, TDFN-EP, TSOC, and TO92

Packages

• 4.0μA (typ) Input Load Current