DS28E01P-100SLASHT中文资料亚德诺数据手册PDF规格书

GENERAL DESCRIPTION

The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations. All memory pages can be write protected, and one page can be put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. Each DS28E01-100 has its own guaranteed unique 64-bit ROM registration number that is factory lasered into the chip. The DS28E01-100 communicates over the single-contact 1-Wire® bus. The communication follows the standard Dallas Semiconductor 1-Wire protocol with the registration number acting as node

address in the case of a multi-device 1-Wire network.

FEATURES

ƒ 1024 bits of EEPROM memory partitioned into four pages of 256 bits

ƒ On-chip 512-bit SHA-1 engine to compute 160-bit Message Authentication Codes (MAC) and to

generate secrets

ƒ Write access requires knowledge of the secret and the capability of computing and transmitting

a 160-bit MAC as authorization

ƒ User-programmable page write-protection for page 0, page 3 or all four pages together

ƒ User-programmable OTP EPROM emulation mode for page 1 (write to 0)

ƒ Communicates to host with a single digital signal at 15.3k bits or 125k bits per second using 1-Wire protocol

ƒ Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise

ƒ Reads and writes over a wide voltage range of 2.8V to 5.25V from -40°C to +85°C

ƒ 6-lead TSOC, 2-lead SFN or solder-bumped chipscale surface mount package

APPLICATIONS

Printer Cartridge Configuration and Monitoring

Medical Sensor Authentication and Calibration

System Intellectual Property Protection