DS21Q42T集成电路（IC）的电信规格书PDF中文资料

DESCRIPTION

The DS21Q42 is an enhanced version of the DS21Q41B Quad T1 Framer. The DS21Q42 contains four framers that are configured and read through a common microprocessor compatible parallel port. Each framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All four framers in the DS21Q42 are totally independent, they do not share a common framing synchronizer.

FEATURES

■ Four T1 DS1/ISDN–PRI/J1 framing transceivers

■ All four framers are fully independent

■ Each of the four framers contain dual two–

■ frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 MHz

■ 8–bit parallel control port that can be used directly on either multiplexed or non– multiplexed buses (Intel or Motorola)

■ Programmable output clocks for Fractional T1

■ Fully independent transmit and receive functionality

■ Integral HDLC controller with 64-byte buffers configurable for FDL or DS0 operation

■ Generates and detects in–band loop codes from 1 to 8 bits in length including CSU loop codes

■ Pin compatible with DS21Q44 E1 Enhanced Quad E1 Framer

■ 3.3V supply with 5V tolerant I/O; low power CMOS

■ Available in 128–pin TQFP package

■ IEEE 1149.1 support