DS21FT40中文资料4x3、12通道、E1成帧器数据手册ADI规格书

描述 Description

The DS21FT40 Four x Three 12-Channel E1 Framer packs three DS21Q44 Quad E1 Framers in one module achieving high capacity in a smaller space. Each independent framer consists of a receive framer and elastic store, and a transmit formatter and elastic store. Transit and receive sides are also completely independent. Control, configuration, and signal data are transmitted between each framer and a microprocessor through a common parallel port that can be flexibly configured for multiplexed or nonmultiplexed connections.
The DS21FT40 is very similar to the DS21FT44 but with a few functions omitted (see p. 4 in the data sheet). It fully meets all of the latest E1 specifications including CCITT/ITU G.704, G.706, G.962, I.431, ETS 300 011, and ETS 300 233.The high-density architecture includes an integrated HDLC controller and JTAG port with 3.3V operation. The HDLC controller can be configured for Sa bits or DS0s and has large receive and transmit buffers that allow a full performance report message to be received or sent without host intervention. Combined with JTAG support, the total functional integration saves external programming effort and board space.
Dallas framers are available in a variety of densities that can combine to exactly meet a variety of application needs. All use interchangeable software, from 4-port to 16-port capacity and from first to latest generation, which enables the implementation of greater line capacity with minimal costs. Complementary T1 and E1 parts are pin-compatible so that one hardware design can support either environment.
The DS21FT40 is designed for telecommunications equipment that requires high port density, low power, and low cost per port. This includes frame relay, switching equipment, ATM, optical and electrical multiplexers, and SONET/SDH communications.

特性 Features

• 12 independent E1 framers in one 27mm x 27mm package
• Each quad can concatenate into one 8.192MHz backplane data stream
• Dual two-frame elastic store slip buffers can connect to backplanes up to 8.192MHz
• Easy access to Si and Sa bits
• Wide range of error counting: bipolar, code, CRC4, FAS, and E-bits
• Integral HDLC controller with 64-byte buffers, configurable for Sa bits or DS0
• IEEE 1149.1 JTAG boundary scan architecture
• 3.3V with 5V-tolerant I/O
• -40°C to +85°C (DS21FT40N)