丝印：DRA821U4TGBALM；Package：FCBGA；DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.48888 Mbytes 页数：254 Pages

TI

德州仪器

丝印：DRA821U4TGBALM；Package：FCBGA；DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.57573 Mbytes 页数：253 Pages

TI

德州仪器

DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.57573 Mbytes 页数：253 Pages

TI

德州仪器

DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.45374 Mbytes 页数：252 Pages

TI

德州仪器

DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.48888 Mbytes 页数：254 Pages

TI

德州仪器