DRA75数据手册TI中文资料规格书

描述 Description

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meetthe intense processing needs of the modern infotainment-enabled automobile experiences.
The device enables Original-Equipment Manufacturers (OEMs) and Original-DesignManufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition,audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximumflexibility of a fully integrated mixed processor solution. The devices also combine programmablevideo processing with a highly integrated peripheral set.
Programmability is provided by dual-core ARM Cortex-A15 RISC CPUs with Neon™ extension,TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The ARMallows developers to keep control functions separate from other algorithms programmed on the DSPand coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the ARM, DSP, and EVEcoprocessor, including C compilers and a debugging interface for visibility into sourcecode.
The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100standard.

特性 Features

• Architecture Designed for Infotainment Applications
• Video, Image, and Graphics Processing Support
• Full-HD Video (1920 × 1080p, 60fps)
• Multiple Video Input and Video Output
• 2D and 3DGraphics

• Dual ARM® Cortex®-A15 Microprocessor Subsystem

• Up to two C66x Floating-Point VLIW DSP
• Fully Object-Code Compatible With C67x and C64x+

• Up to Thirty-two 16 x 16-Bit Fixed-Point Multiplies per Cycle

• Up to 2.5MB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
• Supports up to DDR2-800 and DDR3-1066

• Up to 2GB Supported per EMIF
• Dual ARM® Cortex®-M4 Image Processing Units (IPU)
• Up to Two Embedded Vision Engines (EVEs)
• IVA Subsystem
• Display Subsystem
• Display Controller With DMA Engine and up to ThreePipelines
• HDMI™ Encoder: HDMI1.4a and DVI 1.0 Compliant

• Video Processing Engine (VPE)
• 2D-Graphics Accelerator (BB2D) Subsystem
• Vivante® GC320 Core

• Dual-Core PowerVR® SGX544 3D GPU

• Three Video Input Port (VIP) Modules
• Support for up to 10Multiplexed Input Ports


• General-Purpose Memory Controller (GPMC)

• Enhanced Direct Memory Access (EDMA) Controller

• 2-Port Gigabit Ethernet (GMAC)
• Sixteen 32-Bit General-Purpose Timers

• 32-Bit MPU Watchdog Timer

• Five Inter-Integrated Circuit (I2C) Ports
• HDQ™/1-Wire® Interface
• SATA Interface
• Media Local Bus (MLB) Subsystem
• Ten Configurable UART/IrDA/CIR Modules

• Four Multichannel Serial Peripheral Interfaces (McSPI)
• Quad SPI (QSPI)

• Eight Multichannel Audio Serial Port (McASP) Modules
• SuperSpeed USB 3.0 Dual-Role Device
• Three High-Speed USB 2.0 Dual-Role Devices

• Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)

• PCI-Express® 3.0 Subsystems With Two 5-Gbps Lanes
• One 2-lane Gen2-CompliantPort
• or Two 1-lane Gen2-Compliant Ports
• Dual Controller Area Network (DCAN) Modules
• CAN 2.0B Protocol

• Up to 247 General-Purpose I/O (GPIO) Pins
• Real-Time Clock Subsystem (RTCSS)

• Device security features
• Hardware Crypto accelerators and DMA

• Firewalls
• JTAG® lock
• Secure keys
• SecureROM and boot

• Power, Reset, and Clock Management

• On-Chip Debug With CTools Technology
• 28-nm CMOS Technology

• 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)
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