丝印：DRA；Package：DO-214AA；11 To 170V 600W Surface Mount Transient Voltage Suppressors

Features Glass passivated chip 600W peak pulse power capability with a 10/1000μs waveform, repetitive rate (duty cycle):0.01% High reliability application and automotive grade AEC Q101 qualified Low leakage Uni and Bidirectional unit Excellent clamping capability Very fast response ti

文件：2.90188 Mbytes 页数：6 Pages

UNSEMI

优恩半导体

丝印：DRA；Package：DO-214AA；Surface Mount Transient Voltage Suppressors

文件：277.03 Kbytes 页数：3 Pages

ANOVA

林朋科技

丝印：DRA；Package：DO-214AA；Surface Mount Transient Voltage Suppressors

文件：917.49 Kbytes 页数：3 Pages

LUGUANG

鲁光电子

丝印：DRAO；Package：QFN-22L；28 V/12 A Synchronous EZBuckTM Regulator

General Description The AOZ1269AQI is a high-efficiency, easy-to-use DC/DC synchronous buck regulator that operates up to 28 V. The device is capable of supplying 12 A of continuous output current with an output voltage adjustable down to 0.6 V ±1. A proprietary constant on-time PWM control w

文件：1.69685 Mbytes 页数：15 Pages

AOSMD

万国半导体

丝印：DRA821U2CGBALM；Package：FCBGA；DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.57573 Mbytes 页数：253 Pages

TI

德州仪器

丝印：DRA821U2CGBALM；Package：FCBGA；DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.57573 Mbytes 页数：253 Pages

TI

德州仪器

丝印：DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.45374 Mbytes 页数：252 Pages

TI

德州仪器

丝印：DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.48888 Mbytes 页数：254 Pages

TI

德州仪器

丝印：DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.57573 Mbytes 页数：253 Pages

TI

德州仪器

丝印：DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto™ Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex®- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core • 4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep oper

文件：4.57573 Mbytes 页数：253 Pages

TI

德州仪器