DP8570A中文资料计时器控制外设 (TCP)数据手册TI规格书

描述 Description

The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environments. The circuit's architecture is such that it looks like a contiguous block of memory or I/O ports. The address space is organized as 2 software selectable pages of 32 bytes. This includes the Control Registers, the Clock Counters, the Alarm Compare RAM, the Timers and their data RAM, and the Time Save RAM. Any of the RAM locations that are not being used for their intended purpose may be used as general purpose CMOS RAM.

Time and date are maintained from 1/100 of a second to year and leap year in a BCD format, 12 or 24 hour modes. Day of week, day of month and day of year counters are provided. Time is controlled by an on-chip crystal oscillator requiring only the addition of the crystal and two capacitors. The choice of crystal frequency is program selectable.

Two independent multifunction 10 MHz 16-bit timers are provided. These timers operate in four modes. Each has its own prescaler and can select any of 8 possible clock inputs. Thus, by programming the input clocks and the timer counter values a very wide range of timing durations can be achieved. The range is from about 400 ns (4.915 MHz oscillator) to 65,535 seconds (18 hrs., 12 min.).

Power failure logic and control functions have been integrated on chip. This logic is used by the TCP to issue a power fail

interrupt, and lock out the µp interface. The time power fails may be logged into RAM automatically when VBB > VCC. Additionally, two supply pins are provided. When VBB > VCC, internal circuitry will automatically switch from the main supply to the battery supply. Status bits are provided to indicate initial application of battery power, system power, and low battery detect.



The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environments. The circuit's architecture is such that it looks like a contiguous block of memory or I/O ports. The address space is organized as 2 software selectable pages of 32 bytes. This includes the Control Registers, the Clock Counters, the Alarm Compare RAM, the Timers and their data RAM, and the Time Save RAM. Any of the RAM locations that are not being used for their intended purpose may be used as general purpose CMOS RAM.

Time and date are maintained from 1/100 of a second to year and leap year in a BCD format, 12 or 24 hour modes. Day of week, day of month and day of year counters are provided. Time is controlled by an on-chip crystal oscillator requiring only the addition of the crystal and two capacitors. The choice of crystal frequency is program selectable.

Two independent multifunction 10 MHz 16-bit timers are provided. These timers operate in four modes. Each has its own prescaler and can select any of 8 possible clock inputs. Thus, by programming the input clocks and the timer counter values a very wide range of timing durations can be achieved. The range is from about 400 ns (4.915 MHz oscillator) to 65,535 seconds (18 hrs., 12 min.).

Power failure logic and control functions have been integrated on chip. This logic is used by the TCP to issue a power fail

interrupt, and lock out the µp interface. The time power fails may be logged into RAM automatically when VBB > VCC. Additionally, two supply pins are provided. When VBB > VCC, internal circuitry will automatically switch from the main supply to the battery supply. Status bits are provided to indicate initial application of battery power, system power, and low battery detect.

特性 Features

• Full function real time clock/calendar
• Day of week and day of years counters
• Parallel Resonant Oscillator
• Two 16-bit timers
• Programmable multi-function output
• Power fail features
• Power Supply Bus glitch protection
• On-chip interrupt structure
• Up to 44 bytes of CMOS RAM
• INTR/MFO/T1 pins programmable High/Low and push-pull or open drain
TRI-STATE® is a registered trademark of National Semiconductor Corporation. (size: 390486) WebDIRECT™ Search WebDIRECT™ is a trademark of Coris, Inc., a wholly-owned subsidiary of R.R. Donnelley & Sons Company. How to download and view our Data Sheets Our Data Sheets and other documents are available for downloading in the Portable Document Format (PDF). You can view and print these documents using the Adobe Acrobat Reader. If you do not already have Adobe Acrobat Reader installed and configured on your system, then click here. Copyright © 1995 National Semiconductor Corporation Learn About and Influence The Site