Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly

文件：51.9 Kbytes 页数：5 Pages

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Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly

文件：51.9 Kbytes 页数：5 Pages

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Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly

文件：51.9 Kbytes 页数：5 Pages

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Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs

General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of t

文件：41.27 Kbytes 页数：4 Pages

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Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs

General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of t

文件：41.27 Kbytes 页数：4 Pages

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Quad 2-Input Exclusive-OR Gate

General Description This device contains four independent gates each of which performs the logic exclusive-OR function.

文件：34.5 Kbytes 页数：3 Pages

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Quad 2-Input Exclusive-OR Gate

General Description This device contains four independent gates each of which performs the logic exclusive-OR function.

文件：34.5 Kbytes 页数：3 Pages

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Decade and Binary Counters

General Description The DM7490A monolithic counter contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five. The counter has a gated zero reset and also has gated setto-nine

文件：47.51 Kbytes 页数：5 Pages

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Decade and Binary Counters

General Description The DM7490A monolithic counter contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five. The counter has a gated zero reset and also has gated setto-nine

文件：47.51 Kbytes 页数：5 Pages

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Quad 2-Input NAND Gate

General Description This device contains four independent gates, each of which performs the logic NAND function. Features ■Switching specifications at 50 pF ■Switching specifications guaranteed over full temperature and VCCrange ■Advanced oxide-isolated, ion-implanted Schottky TTL

文件：60.08 Kbytes 页数：5 Pages

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