DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS WITH CLEAR AND COMPLEMENTARY OUTPUTS

文件：91.15 Kbytes 页数：3 Pages

NSC

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DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes 页数：13 Pages

TI

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DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

文件：73.83 Kbytes 页数：3 Pages

Motorola

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DUAL J-K FLIP-FLOPS WITH CLEAR

文件：872.08 Kbytes 页数：17 Pages

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