DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS

文件：102.78 Kbytes 页数：3 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS

文件：102.78 Kbytes 页数：3 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件：300.4 Kbytes 页数：9 Pages

TI

德州仪器

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the

文件：147.33 Kbytes 页数：4 Pages

Motorola

摩托罗拉