DAC2902YSLASH250.B中文资料德州仪器数据手册PDF规格书

FEATURES

125MSPS UPDATE RATE

SINGLE SUPPLY: +3.3V or +5V

HIGH SFDR: 70dB at fOUT = 20MHz

LOW GLITCH: 2pV-s

LOW POWER: 310mW

INTERNAL REFERENCE

POWER-DOWN MODE: 23mW

APPLICATIONS

COMMUNICATIONS:

Base Stations, WLL, WLAN

Baseband I/Q Modulation

MEDICAL/TEST INSTRUMENTATION

ARBITRARY WAVEFORM GENERATORS (ARB)

DIRECT DIGITAL SYNTHESIS (DDS)

DESCRIPTION

The DAC2902 is a monolithic, 12-bit, dual-channel,

high-speed Digital-to-Analog Converter (DAC), and is optimized

to provide high dynamic performance while dissipating

only 310mW.

Operating with high update rates of up to 125MSPS, the

DAC2902 offers exceptional dynamic performance, and

enables the generation of very high output frequencies

suitable for Direct IF applications. The DAC2902 has

been optimized for communications applications in which

separate I and Q data are processed while maintaining

tight gain and offset matching.

Each DAC has a high-impedance differential-current output,

suitable for single-ended or differential analog output

configurations.

The DAC2902 combines high dynamic performance with

a high throughput rate to create a cost-effective solution

for a wide variety of waveform-synthesis applications:

• Pin compatibility between family members provides 10-

bit (DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904)

resolution.

• Pin compatible to the AD9765 dual DAC.

• Gain matching is typically 0.5% of full-scale, and offset

matching is specified at 0.02% max.

• The DAC2902 utilizes an advanced CMOS process; the

segmented architecture minimizes output glitch energy,

and maximizes the dynamic performance.

• All digital inputs are +3.3V and +5V logic compatible.

The DAC2902 has an internal reference circuit, and

allows use of an external reference.

• The DAC2902 is available in a TQFP-48 package, and

is specified over the extended industrial temperature

range of –40°C to +85°C.