DAC12DL3200数据手册开发板套件编程器的评估板-数模转换器（DAC）规格书PDF

描述 Description

The DAC12DL3200 is a very low latency, dual channel, RF sampling digital-to-analog converter (DAC) capable of input and output rates of up to 3.2-GSPS in dual channel mode or 6.4-GSPS in single channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier frequencies approaching 8 GHz when using the multi-Nyquist output modes. The high output frequency range enables direct sampling through C-band (8 GHz) and beyond.

The DAC12DL3200 can be used as an I/Q baseband DAC in dual channel mode. The high sampling rate and output frequency range also makes the DAC12DL3200 capable of arbitrary waveform generation (AWG) and direct digital synthesis (DDS). An integrated DDS block enables single tone and two tone generation on chip.

The DAC12DL3200 has a parallel LVDS interface that consists of up to 48 LVDS pairs and 4 DDR LVDS clocks. A strobe signal is used to synchronize the interface which can be sent over the least significant bit (LSB) or optionally over dedicated strobe LVDS lanes. Each LVDS pair is capable of up to 1.6 Gbps. Multi-device synchronization is supported using a synchronization signal (SYSREF) and is compatible with JESD204B/C clocking devices. SYSREF windowing eases synchronization in multi-device systems.

特性 Features

• 12-bit resolution
• Maximum input and output sample rate:
• Single channel up to 6.4 GSPS
• Dual channel up to 3.2 GSPS

• Multi-Nyquist operating modes:
• Single channel modes: NRZ, RTZ, RF
• Dual channel modes: NRZ, RTZ, RF, 2xRF

• Low latency through device: 6 to 8 ns
• Matching transmit capabilities to the low latency receiver ADC12DL3200
• DAC and ADC combined latency
• Parallel DDR LVDS interface:
• Source synchronous interface to simplify timing:
• 24 or 48 LVDS pairs up to 1.6 Gbps
• 1 LVDS DDR clock per 12-bit bus

• Output frequency range: > 8 GHz
• Full-scale current: 21 mA
• Simplified clocking and synchronization
• SYSREF windowing eases setup and hold times

• On-chip direct digital synthesizer (DDS)
• Single-tone and two-tone sine wave generation
• 32 x 32-bit numerically controlled oscillators
• Fast frequency hopping capability (
• Performance at fOUT = 4.703 GHz, 6.4 GSPS, RF mode
• Output power: –3 dBm
• Noise floor (70 MHz offset): –147 dBc/Hz
• SFDR: 60 dBc

• Power supplies: 1.0 V, 1.8 V, –1.8 V
• Power consumption: 1.49 W (2-ch, RF mode, 3.2 GSPS)
• Package: 256-Ball FCBGA (17x17 mm, 1 mm pitch)