DAC104S085CIMMXSLASHNOPB中文资料德州仪器数据手册PDF规格书

1 Features

1• Qualified for Automotive Applications

• AEC-Q100 Qualified With the Following Results:

– Device Temperature Grade 1: –40°C to 125°C

Ambient Operating Temperature

• Ensured Monotonicity

• Low Power Operation

• Rail-to-Rail Voltage Output

• Power-On Reset to 0 V

• Simultaneous Output Updating

• Wide Power Supply Range (2.7 V to 5.5 V)

• Key Specifications

– Resolution: 10 bits

– INL: ±2 LSB (Maximum)

– DNL: +0.35 / −0.25 LSB (Maximum)

– Settling Time: 6 μs (Maximum)

– Zero Code Error: 15 mV (Maximum)

– Full-Scale Error: −0.75% FS (Maximum)

– Typical Supply Power

– Normal Mode: 1.1 mW (3 V), 2.5 mW (5 V)

– Power Down: 0.3 μW (3 V), 0.8 μW (5 V)

2 Applications

• Battery-Powered Instruments

• Digital Gain and Offset Adjustment

• Programmable Voltage and Current Sources

• Programmable Attenuators

• Automotives

3 Description

The DAC104S085 device is a full-featured, generalpurpose

QUAD 10-bit voltage-output digital-to-analog

converter (DAC) that can operate from a single 2.7-V

to 5.5-V supply and consumes 1.1 mW at 3 V and

2.5 mW at 5 V. The DAC104S085 is packaged in 10-

pin SON and VSSOP packages. The 10-pin SON

package makes the DAC104S085 the smallest QUAD

DAC in its class. The on-chip output amplifier allows

rail-to-rail output swing and the three wire serial

interface operates at clock rates up to 40 MHz over

the entire supply voltage range. Competitive devices

are limited to 25-MHz clock rates at supply voltages

in the 2.7-V to 3.6-V range. The serial interface is

compatible with standard SPI, QSPI, MICROWIRE,

and DSP interfaces.

The reference for the DAC104S085 serves all four

channels and can vary in voltage between 1 V and

VA, providing the widest possible output dynamic

range. The DAC104S085 has a 16-bit input shift

register that controls the outputs to be updated, the

mode of operation, the power-down condition, and

the binary input data. All four outputs can be updated

simultaneously or individually depending on the

setting of the two mode of operation bits.