D5128EETBPGGBU数据手册Kingston中文资料规格书

特性 Features

• Double-data-rate architecture: two data transfers per clock cycle\r
• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture\r
• Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver\r
• DOS is edge-aligned with data for READS; center-aligned with data for WRITES\r
• Differential clock inputs (CK and !CK)\r
• DLL aligns DQ and DOS transitions with CK transitions\r
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS\r
• Data mask (DM) for write data\r
• Posted /CAS by programmable additive latency for better command and data bus efficiency\r
• On-Die Termination (ODD for better signal quality\r
— Synchronous ODT\r
— Dynamic CDT\r
— Asynchronous ODT\r
• Multi Purpose Register (MPR) for pre-defined pattern read out\r
• ZQ calibration for DO drive and ODT\r
• Programmable Partial Array Self-Refresh (PASR)\r
• RESET pin for Power-up sequence and reset function\r
• SRT range: Normal/extended\r
• Programmable Output driver impedance control