Kingston i-Temp DDR3/3L DRAM for embedded applications

KEY FEATURES • Double Data Rate architecture: two data transfers per clock cycle • High-speed data transfer is realized by 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver • DOS

文件：425.79 Kbytes 页数：2 Pages

KINGSTON

金士顿

Kingston DDR3/3L DRAM for embedded applications

KEY FEATURES • Double Data Rate (DDR) architecture: two data transfers per clock cycle • High-speed data transfer is realized by 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：3.59565 Mbytes 页数：2 Pages

KINGSTON

金士顿

Kingston DDR3/3L DRAM for embedded applications

KEY FEATURES • Double Data Rate (DDR) architecture: two data transfers per clock cycle • High-speed data transfer is realized by 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：3.59565 Mbytes 页数：2 Pages

KINGSTON

金士顿

Kingston i-Temp DDR3/3L DRAM for embedded applications

KEY FEATURES • Double Data Rate architecture: two data transfers per clock cycle • High-speed data transfer is realized by 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver • DOS

文件：425.79 Kbytes 页数：2 Pages

KINGSTON

金士顿