CYUSB3015-BZXC中文资料英飞凌数据手册PDF规格书

特性 Features

■ Universal Serial Bus (USB) integration

❐ USB 3.2, Gen 1 and USB 2.0 peripherals compliant with

USB 3.2 Specification Revision 1.0

❐ 5-Gbps SuperSpeed PHY compliant with USB 3.2 Gen 1

❐ Three physical endpoints

❐ Supports UVC, UAC, and USB vendor class protocol

■ General Configurable Interface

❐ Support up to 100 MHz

❐ 8-, 16-, 24-, and 32-bit data bus

❐ Supports Slave FIFO, parallel camera interface

■ 32-bit CPU

❐ ARM926EJ core with 200-MHz operation

❐ 512-KB embedded SRAM

■ Additional connectivity to the following peripherals

❐ SPI boot flash

❐ I2C slaves at 100 kHz / 400 kHz / 1 MHz

■ Selectable clock input frequencies

❐ 19.2, 26, 38.4, and 52 MHz

❐ 19.2-MHz crystal input support

■ Ultra low-power in core power-down mode

❐ Less than 60 μA with VBATT on and 20 μA with VBATT off

■ Independent power domains for core and I/O

❐ Core operation at 1.2 V

❐ SPI operation at 1.8 V to 3.3 V

❐ I2C operation at 1.2 V to 3.3 V

■ Package options

❐ 121-ball, 10-mm  10-mm, 0.8-mm pitch Pb-free ball grid

array (BGA)

❐ See Table 16 for details on SX3 variants

■ EZ-USB™ SX3 configuration utility for configuration of SX3

❐ Works on Windows, macOS, Linux

❐ Example configurations for image sensor, HDMI receiver,

and data applications

❐ Supports programming of SX3 and configure the FPGA

❐ Supports merging of FPGA configuration with SX3

configuration and store in a single SPI flash

■ SX3 Development Kit available for rapid prototyping

❐ Third party HDMI to USB3 capture card kit available from

Cypress design partner