Features

• Graphics subsystem

- Supports 2D and 2.5D (perspective warping, 3D effects) graphics rendering

- Internal color resolution

• 40-bit for RGBA (4 × 10-bit)

• 24-bit for RGB (3 × 8-bit)

- 2048 KB of embedded video RAM memory (VRAM)

- Two video output interfaces supporting a display from

• Parallel RGB (max display size: 1600 × 600 at 80 MHz)

• FPD-link single (max display size: 1920 × 720 at 110 MHz)

- One Capture engine for video input processing for ITU 656 or parallel RGB/YUV or MIPI CSI-2 input

• ITU656 (standard camera capture: up to 800 × 480), multiplexed with RGB interface

• RGB (max capture size 1600 × 600 at 80 MHz) or

• Two-/four-lane MIPI CSI-2 interface (max capture size: 1920 × 720 for two lanes at 110 MHz, 2880 × 1080 for

four lanes at 220 MHz)

- Display warping on-the-fly for HUD applications

- Direct video feed through from capture to display interface with graphics overlay

- Composition engine for scene composition from display layers

- Display engine for video timing generation and display functions

- Drawing engine for acceleration of vector graphics rendering

- Command sequencer for setup and control of the rendering process

- Supports graphics rendering without frame buffers (on-the-fly)

- Single-channel FPD-Link/LVDS interface for up to HD resolution video output

• Sound subsystem

- Four time-division multiplexing (TDM) interfaces

- Two pulse-code modulation-pulse width modulation (PCM-PWM) interfaces

- Up to five sound generator (SG) interfaces

- Two PCM Audio stream mixers with five input streams

- One audio digital-to-analog converter (DAC)

• CPU subsystem

- 240-MHz (max) 32-bit Arm® Cortex®-M7 CPU, with

• Single-cycle multiply

• Single/double-precision floating point unit (FPU)

• 16-KB data cache, 16-KB instruction cache

• Memory protection unit (MPU)

• 64-KB instruction and 64-KB data Tightly-Coupled Memories (TCM)

- 100-MHz 32-bit Arm® Cortex®-M0+ CPU with

• Single-cycle multiply

• Memory protection unit

- Inter-processor communication in hardware

- Four DMA controllers

• Peripheral DMA controller #0 (P-DMA0) with 76 channels

• Peripheral DMA controller #1 (P-DMA1) with 84 channels

• Memory DMA (AHB) controller (M-DMA0) with 8 channels

• Memory DMA (AXI) controller (M-DMA1) with 4 channels

• Integrated memories

- 4160-KB code-flash with an additional 128-KB of work-flash

• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it

• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

• Flash programming through SWD/JTAG interface

- 384-KB SRAM with selectable retention granularity

• Crypto engine[1]

- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

• Using digital signature verification[1]

• Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES[1]: 64-bit blocks, 64-bit key

- Vector unit[1] supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic

Curve (ECC)

- SHA-1/2/3[1]: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC[1]: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

• Functional safety for ASIL-B

- Memory protection unit (MPU)

- Shared memory protection unit (SMPU)

- Peripheral protection unit (PPU)

- Watchdog timer (WDT)

- Multi-counter watchdog timer (MCWDT)

- Low-voltage detector (LVD)

- Brown-out detection (BOD)

- Overvoltage detection (OVD)

- Overcurrent detection (OCD)

- Clock supervisor (CSV)

• Supported in all power modes except Hibernate mode

- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)

• Low-power 2.7-V to 5.5-V operation

- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power

management

- Configurable options for robust BOD

• Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA_ADC

• One threshold level (1.1 V) for BOD on VCCD

• Wakeup support

- Up to four pins to wakeup from Hibernate mode

- Up to 61 GPIO pins to wakeup from DeepSleep mode

- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes

• Clocks

- Internal main oscillator (IMO)

- Internal low-speed oscillator (ILO)

- External crystal oscillator (ECO)

- Watch crystal oscillator (WCO)

- Phase-locked loop (PLL)

- Frequency-locked loop (FLL)

- Low-power external crystal oscillator (LPECO)

• Communication interfaces

- Up to four CAN FD channels

• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and

transceivers

• Compliant to ISO 11898-1:2015

• Supports all the requirements of Bosch CAN FD Specification V1.0 non-ISO CAN FD

• ISO 16845:2015 certificate available

- Up to 12 runtime-reconfigurable serial communication block (SCB) channels, each configurable as I2C, SPI,

or UART

- Up to two independent LIN channels

• LIN protocol compliant with ISO 17987

- Up to two CXPI channels with data rate up to 20 kbps

- 10/100 Mbps Ethernet MAC interface conforming to IEEE-802.3bw

• Supports the following PHY interfaces:

Media-independent interface (MII)

Reduced media-independent interface (RMII)

• Compliant with IEEE-802.1BA for audio video bridging (AVB)

• Compliant with IEEE-1588 precision time protocol (PTP)

• Serial memory interface (SMIF)

- Two SPIs (single, dual, quad, or octal), xSPI interface

- On-the-fly encryption and decryption

- Execute-In-Place (XIP) from external memory

• Timers

- Up to 50 16-bit and 32 32-bit Timer/Counter Pulse-Width modulator (TCPWM) blocks for regular operations

• Up to 12 16-bit counters optimized for motor-control operations (Equivalent to 6 stepper motor-control

[SMC] channels with ZPD and slew rate control capability)

• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PWM_

DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes

- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep

• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,

and so on)

• Real time clock (RTC)

- Year/Month/Date, Day-of-week, Hour:Minute:Second fields

- 12- and 24-hour formats

- Automatic leap-year correction

• I/O

- Up to 135 programmable I/Os

- Four I/O types

• GPIO Standard (GPIO_STD)

• GPIO Enhanced (GPIO_ENH)

• GPIO Stepper Motor Control (GPIO_SMC)

• High-Speed I/O Standard with Low Noise (HSIO_STDLN)

• Power

- Regulators

• Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply

• Two regulators: DeepSleep and Core internal

- PMIC control module

• Programmable analog

- One SAR A/D converter

• Each ADC supports 32 logical channels, with 48 external channels. Any external channel can be connected

to any logical channel in the SAR.

• 12-bit resolution and sampling rates up to 1 Msps

- The ADC also supports six internal analog inputs like

• Bandgap reference to establish absolute voltage levels

• Calibrated diode for junction temperature calculations

• Two AMUXBUS inputs and two direct connections to monitor supply levels

- ADC supports addressing of external multiplexers

- ADC has a sequencer supporting autonomous scanning of configured channels

• Smart I/O

- One smart I/O block, which can perform Boolean operations on signals going to and from I/Os

- Up to eight I/Os (GPIO_STD) supported

• Debug interface

- JTAG controller and interface compliant to IEEE-1149.1-2001

- Arm® SWD (serial wire debug) port

- Supports Arm® Embedded Trace Macrocell (ETM) Trace

• Data trace using SWD

• Instruction and data trace using JTAG

• Compatible with industry-standard tools

- GHS MULTI or IAR EWARM for code development and debugging

• Packages

- 272-BGA, 16 × 16 × 1.7 mm (max), 0.8-mm ball pitch

- 216-TEQFP, 24 × 24 × 1.6 mm (max), 0.4-mm ball pitch