CY7C43684中文资料赛普拉斯数据手册PDF规格书

Functional Description

The CY7C436X4 is a monolithic, high-speed, low-power, CMOS Bidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 133 MHz and has read access times as fast as 6 ns. Two independent 1K/4K/16K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big or Little Endian configurations.

特性 Features

• High-speed, low-power, bidirectional, First-In, First-Out (FIFO) memories with bus matching capabilities

• 1K x36 x2 (CY7C43644)

• 4K x36 x2 (CY7C43664)

• 16K x36 x2 (CY7C43684)

• 0.35-micron CMOS for optimum speed/power

• High-speed 133-MHz operation (7.5 ns read/write cycle times)

• Low power

— ICC = 100 mA

— ISB = 10 mA

• Fully asynchronous and simultaneous read and write operation permitted

• Mailbox bypass register for each FIFO

• Parallel and Serial Programmable Almost-Full and Almost-Empty flags

• Retransmit function

• Standard or FWFT mode user selectable

• Partial Reset

• Big or Little Endian format for word or byte bus sizes

• 128-pin TQFP packaging

• Easily expandable in width and depth