CY7C1564XV18-366BZC集成电路（IC）的存储器规格书PDF中文资料

Functional Description

The CY7C1562XV18, and CY7C1564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR® II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/Os devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

特性 Features

■ Separate independent read and write data ports ❐ Supports concurrent transactions

■ 450 MHz clock for high bandwidth

■ Two-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR™-II+ Xtreme operates with 2.5 cycle read latency when DOFF is asserted HIGH

■ Operates similar to QDR-I device with 1 cycle read latency when DOFF is asserted LOW

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

■ Core VDD = 1.8 V± 0.1 V; I/Os VDDQ = 1.4 V to 1.6 V ❐ Supports 1.5 V I/O supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase-Locked Loop (PLL) for accurate data placement