2M x 36/4M x 18/1M x 72 Flow-through SRAM

Functional Description[1] The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip cou

文件：638.57 Kbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

文件：1.27217 Mbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2M x 36/4M x 18/1M x 72 Flow-through SRAM

Functional Description[1] The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip cou

文件：638.57 Kbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2M x 36/4M x 18/1M x 72 Flow-through SRAM

Functional Description[1] The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip cou

文件：638.57 Kbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2M x 36/4M x 18/1M x 72 Flow-through SRAM

Functional Description[1] The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip cou

文件：638.57 Kbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

2M x 36/4M x 18/1M x 72 Flow-through SRAM

Functional Description[1] The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip cou

文件：638.57 Kbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

文件：1.27217 Mbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

文件：1.27217 Mbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

文件：1.27217 Mbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

文件：1.27217 Mbytes 页数：30 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司