CY7C1462AV25集成电路（IC）的存储器规格书PDF中文资料

CY7C1462AV25属于集成电路（IC）的存储器。由赛普拉斯半导体公司制造生产的CY7C1462AV25存储器存储器是集成电路上用作数据存储设备的半导体器件。这些器件分为非易失性或易失性两种，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、闪存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。这些器件的存储容量为 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、单线、SPI、UFS、Xccela 总线和 1-线。

Functional Description

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are pin-compatible and functionally equivalent to ZBT devices.

特性 Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200 and 167 MHz

• Internally self-timed output buffer control to eliminate the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined operation

• Byte Write capability

• 2.5V core power supply

• 2.5V/1.8V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• CY7C1460AV25, CY7C1462AV25 available in

JEDEC-standard lead-free 100-pin TQFP package,

lead-free and non-lead-free 165-ball FBGA package.

CY7C1464AV25 available in lead-free and non-lead-free

209-ball FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option