36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

文件：395.4 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

文件：513.48 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

文件：513.48 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

文件：395.4 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

文件：395.4 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

文件：513.48 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司