CY7C1422KV18中文资料赛普拉斯数据手册PDF规格书

Functional Description

The CY7C1422KV18, CY7C1429KV18, CY7C1423KV18, and CY7C1424KV18 are 1.8 V synchronous pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus required with common I/O devices.

特性 Features

■ 36 Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)

■ 333 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed systems

■ Synchronous internally self timed writes

■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH

■ Operates similar to DDR I device with 1 cycle read latency when DOFF is asserted LOW

■ 1.8 V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4 V to VDD)

❐ Supports both 1.5 V and 1.8 V IO supply

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement