256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

文件：307.76 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

文件：307.76 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Features • Fast access times: 2.5 ns

文件：307.76 Kbytes 页数：27 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Pipelined SRAM

Functional Description\nThe Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns\n• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150 MHz\n• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns\n• Optimal for performance (two cycle chip deselect, depth\n   expansion without wait state)\n• 3.3V –5% and +10% power supply\n• 3.;

Infineon

英飞凌